1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for fabricating an asymmetric semiconductor device, such as, an asymmetric metal-oxide-semiconductor field effect transistor (MOSFET).
2. Description of Related Art
An asymmetric semiconductor device is defined as a device having asymmetric doped regions. For example, an asymmetric MOSFET features that its gate-to-source overlap capacitance is different from its gate-to-drain overlap capacitance. The gate-to-drain overlap capacitance frequently acts as a component of the input capacitance and the output capacitance, hence is usually a serious performance detractor in lightly loaded CMOS circuits. In some cases, the gate-to-drain capacitance contribution is even nearly doubled from its original value due to the Miller Effect. Therefore, asymmetric MOSFETs play an important role in circuit performance improvement.
In the prior art, asymmetric semiconductor devices are fabricated through complicated implantation engineering and/or integration modification, instead of thermal annealing. It is because the conventional thermal annealing techniques are all immersion-type techniques, in which all doped regions are annealed under the same temperature. Accordingly, an effective method for fabricating asymmetric semi-conductor devices is highly desired.